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| 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator ADP122/ADP123 FEATURES Input voltage supply range: 2.3 V to 5.5 V 300 mA maximum output current Fixed and adjustable output voltage versions Very low dropout voltage: 85 mV at 300 mA load Low quiescent current: 45 A at no load Low shutdown current: <1 A Initial accuracy: 1% accuracy Up to 31 fixed-output voltage options available from 1.75 V to 3.3 V Adjustable-output voltage range 0.8 V to 5.0 V (ADP123) Excellent PSRR performance: 60 dB at 100 kHz Excellent load/line transient response Optimized for small 1.0 F ceramic capacitors Current limit and thermal overload protection Logic controlled enable Compact, 5-lead TSOT package TYPICAL APPLICATION CIRCUIT VIN = 2.3V TO 5.5V 1 VOUT = 1.8V VIN VOUT 5 CIN 1F 2 ADP122 GND COUT 1F 3 EN NC 4 OFF Figure 1. ADP122 with Fixed Output Voltage VIN = 2.3V TO 5.5V 1 VOUT = 0.5V(1 + R1/R2) VIN VOUT 5 CIN 1F 2 ADP123 GND R1 COUT 1F ON OFF 3 EN ADJ 4 APPLICATIONS Digital camera and audio devices Portable and battery-powered equipment Automatic meter reading (AMR) meters GPS and location management units Medical instrumentation Point-of-sale equipment Figure 2. ADP 123 with Adjustable Output Voltage GENERAL DESCRIPTION The ADP122/ADP123 are low quiescent current, low dropout linear regulators. They are designed to operate from an input voltage between 2.3 V and 5.5 V and to provide up to 300 mA of output current. The low 85 mV dropout voltage at a 300 mA load improves efficiency and allows operation over a wide input voltage range. The low 170 A of quiescent current at full load makes the ADP122 ideal for battery-operated portable equipment. The ADP122 is capable of 31 fixed output voltages from 1.75 V to 3.3 V. The ADP123 is the adjustable version of the device and allows the output voltage to be set between 0.8 V and 5.0 V by an external voltage divider. The ADP122/ADP123 are specifically designed for stable operation with tiny 1 F ceramic input and output capacitors to meet the requirements of high performance, space constrained applications. The ADP122/ADP123 have an internal soft start that gives a constant start-up time of 350 s. Short-circuit protection and thermal overload protection circuits prevent damage in adverse conditions. The ADP122/ADP123 are available in a tiny, 5-lead TSOT package for the smallest footprint solution to meet a variety of portable applications. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved. 08399-002 R2 08399-001 ON ADP122/ADP123 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Typical Application Circuit ............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Recommended Specifications ..................................................... 4 Absolute Maximum Ratings............................................................ 5 Thermal Data ................................................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution .................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ..............................................7 Theory of Operation ...................................................................... 11 Applications Information .............................................................. 12 Capacitor Selection .................................................................... 12 Undervoltage Lockout ............................................................... 13 Enable Feature ............................................................................ 13 Current Limit and Thermal Overload Protection ................. 14 Thermal Considerations............................................................ 14 Junction Temperature Calculations ......................................... 15 Printed Circuit Board Layout Considerations ....................... 16 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18 REVISION HISTORY 10/09--Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADP122/ADP123 SPECIFICATIONS Unless otherwise noted, VIN = (VOUT + 0.3 V) or 2.3 V, whichever is greater; ADJ connected to VOUT; IOUT = 10 mA; CIN = 1.0 F; COUT = 1.0 F; TA = 25C. Table 1. Parameter INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT 1 Symbol VIN IGND Test Conditions IOUT = 0 A IOUT = 0 A, TJ = -40C to +125C IOUT = 1 mA IOUT = 1 mA, TJ = -40C to +125C IOUT = 150 mA IOUT = 150 mA, TJ = -40C to +125C IOUT = 300 mA IOUT = 300 mA, TJ = -40C to +125C EN = GND EN = GND, TJ = -40C to +125C IOUT = 10 mA 100 A < IOUT < 300 mA, VIN = (VOUT + 0.5 V) to 5.5 V, TJ = -40C to +125C IOUT = 10 mA 100 A < IOUT < 300 mA, VIN = 2.3 V to 5.5 V, TJ = -40C to +125C VIN = VIN = 2.3 V to 5.5 V, TJ = -40C to +125C IOUT = 1 mA to 300 mA IOUT = 1 mA to 300 mA , TJ = -40C to +125C 2.3 V VIN 5.5 V, ADJ connected to VOUT IOUT = 10 mA, VOUT > 2.3 V IOUT = 10 mA, TJ = -40C to +125C IOUT = 150 mA, VOUT > 2.3 V IOUT = 150 mA, TJ = -40C to +125C IOUT = 300 mA, VOUT > 2.3V IOUT = 300 mA, TJ = -40C to +125C VOUT = 3.0 V 350 TJ rising -1 -2 0.495 0.490 -0.05 0.0005 0.001 15 3 5 45 75 85 150 350 500 150 15 1.2 0.4 0.1 1 2.1 1.5 125 650 0.500 0.500 Min 2.3 Typ 45 105 60 120 130 190 170 240 0.1 1 +1 +1.5 0.505 0.5075 +0.05 Max 5.5 Unit V A A A A A A A A A A % % V V %/V %/mA %/mA nA mV mV mV mV mV mV s mA C C V V A A V V mV SHUTDOWN CURRENT OUTPUT VOLTAGE ACCURACY 2 Fixed Output ISD VOUT Adjustable Output LINE REGULATION LOAD REGULATION 3 ADJ INPUT BIAS CURRENT DROPOUT VOLTAGE 4 VOUT/VIN VOUT/IOUT ADJI-BIAS VDROPOUT START-UP TIME 5 CURRENT LIMIT THRESHOLD 6 THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis EN INPUT EN Input Logic High EN Input Logic Low EN Input Leakage Current UNDERVOLTAGE LOCKOUT Input Voltage Rising Input Voltage Falling Hysteresis tSTART-UP ILIMIT TSSD TSSD-HYS VIH VIL VI-LEAKAGE UVLO UVLORISE UVLOFALL UVLOHYS 2.3 V VIN 5.5 V 2.3 V VIN 5.5 V EN = VIN or GND EN = VIN or GND, TJ = -40C to +125C TJ = -40C to +125C TJ = -40C to +125C TA = 25C Rev. 0 | Page 3 of 20 ADP122/ADP123 Parameter OUTPUT NOISE Symbol OUTNOISE Test Conditions 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.2 V 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 1.8 V 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 2.5 V 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 3.3 V 10 Hz to 100 kHz, VIN = 5.5 V, VOUT = 4.2 V 10 kHz, VOUT = 3.3 V 10 kHz, VOUT = 2.5 V 10 kHz, VOUT = 1.8 V 100 kHz, VOUT = 3.3 V 100 kHz, VOUT = 2.5 V 100 kHz, VOUT = 1.8 V Min Typ 25 35 45 55 65 60 60 60 60 60 60 Max Unit V rms V rms V rms V rms dB dB dB dB dB dB POWER SUPPLY REJECTION RATIO (VIN = VOUT + 0.5 V) PSRR 1 2 The current from the external resistor divider network in the case of adjustable voltage output (as with the ADP123) should be subtracted from the ground current measured. Accuracy when VOUT is connected directly to ADJ. When VOUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances of the resistors used. 3 Based on an endpoint calculation using 1 mA and 300 mA loads. 4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages greater than 2.3 V. 5 Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of its nominal value. 6 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.3 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.3V, or 2.97 V. RECOMMENDED SPECIFICATIONS Table 2. Parameter Minimum Input and Output Capacitance 1 Capacitor ESR 1 Symbol CAPMIN RESR Test Conditions TA = -40C to +125C TA = -40C to +125C Min 0.70 0.001 Typ Max Unit F 1 The minimum input and output capacitance should be greater than 0.70 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use with any LDO. Rev. 0 | Page 4 of 20 ADP122/ADP123 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VIN to GND ADJ to GND EN to GND VOUT to GND Storage Temperature Range Operating Ambient Temperature Range Operating Junction Temperature Soldering Conditions Rating -0.3 V to +6.5 V -0.3 V to +4 V -0.3 V to +6.5 V -0.3 V to VIN -65C to +150C -40C to +85C -40C to +125C JEDEC J-STD-020 application and board layout. In applications in which high maximum power dissipation exists, close attention to thermal board design is required. The value of JA may vary, depending on PCB material, layout, and environmental conditions. The specified values of JA are based on a 4-layer, 4 inch x 3 inch circuit board. Refer to JESD51-7 for detailed information on the board construction JB is the junction-to-board thermal characterization parameter and is measured in C/W. The JB of the package is based on modeling and calculation using a 4-layer board. The Guidelines for Reporting and Using Package Thermal Information: JESD51-12 states that thermal characterization parameters are not the same as thermal resistances. JB measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, JB. Therefore, JB thermal paths include convection from the top of the package as well as radiation from the package--factors that make JB more useful in real-world applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the formula TJ = TB + (PD x JB) Refer to JESD51-8 and JESD51-12 for more detailed information about JB. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP122/ADP123 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ will remain within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (JA). Maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) using the formula TJ = TA + (PD x JA) The junction-to-ambient thermal resistance (JA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the THERMAL RESISTANCE JA and JB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 5-Lead TSOT JA 170 JB 43 Unit C/W ESD CAUTION Rev. 0 | Page 5 of 20 ADP122/ADP123 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VIN 1 GND 2 EN 3 ADP122 TOP VIEW (Not to Scale) 5 VOUT VIN 1 GND 2 ADP123 TOP VIEW (Not to Scale) 5 VOUT 4 NC 08399-004 EN 3 4 ADJ NC = NO CONNECT Figure 3. ADP122 Fixed Output Pin Configuration Figure 4. ADP123 Adjustable Output Pin Configuration Table 5. Pin Function Descriptions Pin No. ADP122 ADP123 1 1 2 2 3 3 N/A 4 5 4 N/A 5 Mnemonic VIN GND EN ADJ NC VOUT Description Regulator Input Supply. Bypass VIN to GND with a capacitor of at least 1 F. Ground. Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to VIN. Output Voltage Adjust Input. Connect the midpoint of an external divider from VOUT to GND to this pin to set the output voltage. Not Connected Internally. Regulated Output Voltage. Bypass VOUT to GND with a capacitor of at least 1 F. Rev. 0 | Page 6 of 20 08399-003 ADP122/ADP123 TYPICAL PERFORMANCE CHARACTERISTICS VIN = 3.6 V, VOUT = 3.3 V, IOUT = 10 mA, CIN = 1.0 F, COUT = 1.0 F, TA = 25C, unless otherwise noted. 3.300 3.295 250 200 GROUND CURRENT (A) 3.290 3.285 VOUT (V) 3.280 3.275 3.270 3.265 08399-005 IOUT = 300mA 150 IOUT = 200mA IOUT = 100mA 100 IOUT = 10mA 50 IOUT = 100A IOUT = 1mA IOUT = 10mA IOUT = 100mA IOUT = 200mA IOUT = 300mA IOUT = 100A IOUT = 1mA -40 -5 25 85 JUNCTION TEMPERATURE (C) 125 -40 -5 25 85 JUNCTION TEMPERATURE (C) 125 Figure 5. Output Voltage vs. Junction Temperature Figure 8. Ground Current vs. Junction Temperature 3.2945 3.2940 3.2935 200 180 160 GROUND CURRENT (A) 3.2930 VOUT (V) 140 120 100 80 60 40 20 3.2925 3.2920 3.2915 3.2910 3.2905 3.2900 08399-006 1 10 IOUT (mA) 100 1000 0.1 1 10 IOUT (mA) 100 1000 Figure 6. Output Voltage vs. Load Current Figure 9. Ground Current vs. Load Current 3.296 200 180 IOUT = 300mA 3.294 160 GROUND CURRENT (A) 3.292 140 120 100 80 60 40 20 IOUT = 200mA VOUT (V) 3.290 IOUT = 100mA IOUT = 10mA IOUT = 1mA IOUT = 100A 3.288 3.286 08399-007 3.6 3.8 4.0 4.2 4.4 4.6 VIN (V) 4.8 5.0 5.2 5.4 3.8 4.0 4.2 4.4 4.6 VIN (V) 4.8 5.0 5.2 5.4 Figure 7. Output Voltage vs. Input Voltage Figure 10. Ground Current vs. Input Voltage Rev. 0 | Page 7 of 20 08399-010 3.284 IOUT = 100A IOUT = 1mA IOUT = 10mA IOUT = 100mA IOUT = 200mA IOUT = 300mA 0 3.6 08399-009 3.2895 0.1 0 08399-008 3.260 0 ADP122/ADP123 0.50 0.45 3.35 3.30 3.25 IOUT IOUT IOUT IOUT = 10mA = 100mA = 150mA = 300mA SHUTDOWN CURRENT (A) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 -50 VIN = 3.6V VIN = 3.8V VIN = 4.2V VIN = 4.4V VIN = 5.0V VIN = 5.2V VIN = 5.4V VIN = 5.5V VOUT (V) 08399-011 3.20 3.15 3.10 3.05 -25 0 25 50 75 TEMPERATURE (C) 100 125 3.10 3.15 3.20 3.25 VIN (V) 3.30 3.35 3.40 Figure 11. Shutdown Current vs. Temperature at Various Input Voltages Figure 14. Output Voltage vs. Input Voltage (in Dropout) 70 60 -10 -20 -30 IOUT = 100A IOUT = 1mA IOUT = 10mA IOUT = 100mA IOUT = 200mA IOUT = 300mA 50 DROPOUT (mV) -40 40 30 PSRR (dB) -50 -60 -70 20 -80 -90 08399-012 08399-015 10 VIN = VOUT + 0.5V VRIPPLE = 50mV CIN = COUT 1F 10 100 1k 10k 100k 1M 0 1 10 IOUT (mA) 100 1000 -100 FREQUENCY (Hz) 10M Figure 12. Dropout Voltage vs. Load Current Figure 15. Power Supply Rejection Ratio vs. Frequency, VOUT = 2.8 V, VIN = 3.3 V 450 400 350 300 250 200 150 100 50 0 3.05 IOUT = 10mA IOUT = 100mA IOUT = 150mA IOUT = 300mA 3.10 3.15 3.20 3.25 VIN (V) 3.30 3.35 3.40 3.45 08399-014 -10 -20 -30 -40 IOUT = 100A IOUT = 1mA IOUT = 10mA IOUT = 100mA IOUT = 200mA IOUT = 300mA PSRR (dB) IGND (A) -50 -60 -70 -80 -90 -100 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 13. Ground Current vs. Input Voltage (in Dropout) Figure 16. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V, VIN = 3.8 V Rev. 0 | Page 8 of 20 08399-016 VIN = VOUT + 0.5V VRIPPLE = 50mV CIN = COUT 1F 08399-013 3.00 3.05 ADP122/ADP123 -10 -20 -30 -40 IOUT = 100A IOUT = 1mA IOUT = 10mA IOUT = 100mA IOUT = 200mA IOUT = 300mA 5 VOUT = 4.2V 4 NOISE (v/Hz) VOUT = 3.3V PSRR (dB) -50 -60 -70 -80 -90 -100 10 3 2 08399-017 0 10 100 1k FREQUENCY (Hz) 10k 100 1k 10k 100k 1M 10M 100k FREQUENCY (Hz) Figure 17. Power Supply Rejection Ratio vs. Frequency, VOUT = 4.2 V, VIN = 4.7 V Figure 20. Output Noise Spectrum -10 -20 -30 -40 70 65 60 VOUT = 4.2V RMS NOISE (V) PSRR (dB) -50 -60 -70 -80 -90 -100 10 VOUT = 2.8V, VOUT = 3.3V, VOUT = 4.2V, VOUT = 2.8V, VOUT = 3.3V, VOUT = 4.2V, IOUT = 1mA IOUT = 1mA IOUT = 1mA IOUT = 300mA IOUT = 300mA IOUT = 300mA VOUT = 3.3V 55 50 45 40 VOUT = 2.8V 08399-018 100 1k 10k 100k 1M 10M 30 0.001 0.01 0.1 FREQUENCY (Hz) 1 IOUT (mA) 10 100 1000 Figure 18. Power Supply Rejection Ratio vs. Frequency, Various Output Voltages and Load Currents Figure 21 Output Noise vs. Load Current and Output Voltage -10 -20 -30 -40 VIN = 3.1V, VIN = 3.3V, VIN = 3.8V, VIN = 4.8V, VIN = 3.1V, VIN = 3.3V, VIN = 3.8V, VIN = 4.8V, IOUT = 1mA IOUT = 1mA IOUT = 1mA IOUT = 1mA IOUT = 300mA IOUT = 300mA IOUT = 300mA IOUT = 300mA IOUT 1mA TO 300mA LOAD STEP 1 PSRR (dB) -50 -60 2 VOUT -70 -80 -90 -100 10 100 1k 10k 100k 1M FREQUENCY (Hz) VRIPPLE = 50mV CIN = COUT 1F 08399-019 10M CH1 200mA B W CH2 50.0mV B W M 40.0s A CH1 T 10.20% 196mA Figure 19. Power Supply Rejection Ratio vs. Headroom Voltage (VIN - VOUT) Figure 22. Load Transient Response, COUT = 1 F Rev. 0 | Page 9 of 20 08399-022 VIN = 3.7V VOUT = 3.3V 08399-021 VIN = VOUT + 0.5V VRIPPLE = 50mV CIN = COUT 1F 35 08399-020 VIN = VOUT + 0.5V VRIPPLE = 50mV CIN = COUT 1F 1 VOUT = 2.8V ADP122/ADP123 IOUT 1mA TO 300mA LOAD STEP 1 VIN 4V TO 4.5V VOLTAGE STEP 2 VOUT 2 VOUT 1 08399-023 CH1 200mA B W CH2 20.0mV B W M 40.0s A CH1 T 10.40% 196mA CH1 1.00V BW CH2 2.00mV B W M 10.0s A CH3 T 9.600% 2.04V Figure 23. Load Transient Response, COUT = 4.7 F Figure 25. Line Transient Response, Load Current = 300 mA VIN 4V TO 4.5V VOLTAGE STEP 2 VOUT 1 CH1 1.00V BW CH2 2.00mV B W M 10.0s A CH3 T 10.00% 2.04V Figure 24. Line Transient Response, Load Current = 1 mA 08399-024 Rev. 0 | Page 10 of 20 08399-025 VIN = 3.7V VOUT = 3.3V ADP122/ADP123 THEORY OF OPERATION The ADP122/ADP123 are low quiescent current, low-dropout linear regulators that operate from 2.3 V to 5.5 V and can provide up to 300 mA of output current. Drawing a low 170 A of quiescent current (typical) at full load makes the ADP122/ADP123 ideal for battery-operated portable equipment. Shutdown current consumption is typically 100 nA. Optimized for use with small 1 F ceramic capacitors, the ADP122/ADP123 provide excellent transient performance. Internally, the ADP122/ADP123 consist of a reference, an error amplifier, a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. The adjustable ADP123 has an output voltage range of 0.8 V to 5.0 V. The output voltage is set by the ratio of two external resistors, as shown in Figure 2. The device servos the output to maintain the voltage at the ADJ pin at 0.5 V referenced to ground. The current in R1 is then equal to 0.5 V/R2 and the current in R1 is the current in R2 plus the ADJ pin bias current. The ADJ pin bias current, 15 nA at 25C, flows through R1 into the ADJ pin. The output voltage can be calculated using the equation: VOUT = 0.5 V(1 + R1/R2) + (ADJI-BIAS)(R1) The value of R1 should be less than 200 k to minimize errors in the output voltage caused by the ADJ pin bias current. For example, when R1 and R2 each equal 200 k, the output voltage is 1.0 V. The output voltage error introduced by the ADJ pin bias current is 3 mV or 0.3%, assuming a typical ADJ pin bias current of 15 nA at 25C. ADJ EN SHUTDOWN 0.5V REFERENCE 08399-122 Note that in shutdown, the output is turned off and the divider current is 0. The ADP122/ADP123 use the EN pin to enable and disable the VOUT pin under normal operating conditions. When EN is high, VOUT turns on; when EN is low, VOUT turns off. For automatic startup, EN can be tied to VIN. ADP122 VIN VOUT GND SHORT CIRCUIT, UVLO AND THERMAL PROTECT R1 EN SHUTDOWN 0.5V REFERENCE R2 08399-121 NOTES 1. R1 AND R2 ARE INTERNAL RESISTORS, AVAILABLE ON THE ADP122 ONLY. Figure 26. ADP122 Internal Block Diagram (Fixed Output) ADP123 VIN VOUT GND SHORT CIRCUIT, UVLO AND THERMAL PROTECT Figure 27. ADP123 Internal Block Diagram (Adjustable Output) Rev. 0 | Page 11 of 20 ADP122/ADP123 APPLICATIONS INFORMATION CAPACITOR SELECTION Output Capacitor The ADP122/ADP123 are designed for operation with small, space-saving ceramic capacitors, but these devices can function with most commonly used capacitors as long as care is taken to ensure an appropriate effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 0.70 F capacitance with an ESR of 1 or less is recommended to ensure stability of the ADP122/ADP123. The transient response to changes in load current is also affected by the output capacitance. Using a larger value of output capacitance improves the transient response of the ADP122/ADP123 to dynamic changes in load current. Figure 28 and Figure 29 show the transient responses for output capacitance values of 1 F and 4.7 F, respectively. IOUT 1mA TO 300mA LOAD STEP 1 Input and Output Capacitor Properties Any good quality ceramic capacitors can be used with the ADP122/ ADP123, as long as the capacitor meets the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have an adequate dielectric to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. Using an X5R or X7R dielectric with a voltage rating of 6.3 V or 10 V is recommended. However, using Y5V and Z5U dielectrics is not recommended for any LDO, due to their poor temperature and dc bias characteristics. Figure 30 depicts the capacitance vs. capacitor voltage bias characteristics of a 0603, 1 F, 6.3 V X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and the voltage rating. In general, a capacitor in a larger package or of a higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about 15% over the -40C to +85C temperature range and is not a function of package or voltage rating. 1.10 1.05 2 VOUT 1.00 CAPACITANCE (F) 0.95 0.90 0.85 0.80 08399-030 CH1 200mA BW CH2 50.0mV B W M 400ns A CH1 T 14.80% 196mA Figure 28. Output Transient Response, COUT = 1 F 08399-026 VIN = 3.7V VOUT = 3.3V 0.75 IOUT 1mA TO 300mA LOAD STEP 1 0.70 0 1 2 3 4 5 6 7 BIAS VOLTAGE (V) Figure 30. Capacitance vs. Capacitor Voltage Bias Characteristics 2 Equation 1 can be used to determine the worst-case capacitance, accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = C x (1 - TEMPCO) x (1 - TOL) VOUT VIN = 3.7V VOUT = 3.3V CH1 200mA B W (1) CH2 20.0mV M 400ns A CH1 T 15.00% 196mA where: CEFF is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and C is 0.96 F at 4.2 V from the graph in Figure 30. Substituting these values in Equation 1 yields CEFF = 0.96 F x (1 - 0.15) x (1 - 0.1) = 0.734 F Figure 29. Output Transient Response, COUT = 4.7 F Input Bypass Capacitor Connecting a 1 F capacitor from VIN to GND reduces the circuit sensitivity to the printed circuit board (PCB) layout, especially when a long input trace or high source impedance is encountered. If greater than 1 F of output capacitance is required, the input capacitor should be increased to match it. 08399-027 Rev. 0 | Page 12 of 20 ADP122/ADP123 Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP122/ADP123, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors are evaluated for each application. ENABLE THRESHOLDS (V) 1.1 1.0 RISING 0.9 0.8 FALLING 0.7 UNDERVOLTAGE LOCKOUT The ADP122/ADP123 have an internal undervoltage lockout circuit that disables all inputs and the output when the input voltage is less than approximately 2 V. This ensures that the ADP122/ADP123 inputs and the output behave in a predictable manner during power-up. 0.6 2.7 3.2 ENABLE FEATURE The ADP122/ADP123 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. As shown in Figure 31, when a rising voltage on EN crosses the active threshold, VOUT turns on. Conversely, when a falling voltage on EN crosses the inactive threshold, VOUT turns off. 3.5 3.7 4.2 VIN(V) 4.7 5.2 Figure 32. Typical EN Pin Thresholds vs. Input Voltage 3.0 The ADP122/ADP123 utilize an internal soft start to limit the in-rush current when the output is enabled. The start-up time for the 2.8 V option is approximately 350 s from the time the EN active threshold is crossed to when the output reaches 90% of its final value. As shown in Figure 33, the start-up time is dependent on the output voltage setting and increases slightly as the output voltage increases. VIN = 5V VOUT = 4.2V VOUT = 3.3V 2.5 VOUT 2.0 1.5 VOUT = 2.8V 1.0 08399-230 0.5 0 0 0.2 0.4 0.6 0.8 VEN 1.0 1.2 1.4 1.6 1 2 Figure 31. Typical EN Pin Operation CH1 1.00V CH2 1.00V As shown in Figure 31, the EN pin has built-in hysteresis. This prevents on/off oscillations that may occur due to noise on the EN pin as it passes through the threshold points. The active and inactive thresholds of the EN pin are derived from the VIN voltage. Therefore, these thresholds vary as the input voltage changes. Figure 32 shows typical EN active and inactive thresholds when the VIN voltage varies from 2.3 V to 5.5 V. M200s A CH1 T 600.000s 3.08V Figure 33. Typical Start-Up Time Rev. 0 | Page 13 of 20 08399-033 08399-034 0.5 2.2 ADP122/ADP123 CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION The ADP122/ADP123 are protected from damage due to excessive power dissipation by current and thermal overload protection circuits. The ADP122/ADP123 are designed to limit the current when the output load reaches 500 mA (typical). When the output load exceeds 500 mA, the output voltage is reduced to maintain a constant current limit. Thermal overload protection is included, which limits the junction temperature to a maximum of 150C typical. Under extreme conditions (that is, high ambient temperature and power dissipation), when the junction temperature starts to rise above 150C, the output is turned off, reducing output current to zero. When the junction temperature cools to less than 135C, the output is turned on again and the output current is restored to its nominal value. Consider the case where a hard short from VOUT to GND occurs. At first, the ADP122/ADP123 limit the current so that only 500 mA is conducted into the short. If self-heating causes the junction temperature to rise above 150C, thermal shutdown activates, turning off the output and reducing the output current to zero. When the junction temperature cools to less than 135C, the output turns on and conducts 500 mA into the short, again causing the junction temperature to rise above 150C. This thermal oscillation between 135C and 150C results in a current oscillation between 500 mA and 0 mA that continues as long as the short remains at the output. Current and thermal limit protections are intended to protect the device from damage due to accidental overload conditions. For reliable operation, the device power dissipation must be externally limited so that the junction temperature does not exceed 125C. The junction temperature of the ADP122/ADP123 can be calculated from the following equation: TJ = TA + (PD x JA) where: TA is the ambient temperature. PD is the power dissipation in the die, given by PD = [(VIN - VOUT) x ILOAD] + (VIN x IGND) where: ILOAD is the load current. IGND is the ground current. VIN and VOUT are input and output voltages, respectively. The power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation can be simplified as follows: TJ = TA + {[(VIN - VOUT) x ILOAD] x JA} (4) As shown in Equation 4, for a given ambient temperature, inputto-output voltage differential, and continuous load current, there exists a minimum copper size requirement for the PCB to ensure that the junction temperature does not rise above 125C. Figure 34 through Figure 40 show junction temperature calculations for different ambient temperatures, load currents, VIN to VOUT differentials, and areas of PCB copper. In cases where the board temperature is known, the thermal characterization parameter, JB, can be used to estimate the junction temperature rise. The maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (PD) using the formula TJ = TB + (PD x JB) (5) (3) (2) THERMAL CONSIDERATIONS To guarantee reliable operation, the junction temperature of the ADP122/ADP123 must not exceed 125C. To ensure that the junction temperature is less than this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (JA). The value of JA is dependent on the package assembly compounds used and the amount of copper to which the GND pins of the package are soldered on the PCB. Table 6 shows typical JA values of the 5-lead TSOT package for various PCB copper sizes. Table 6. Typical JA Values for Specified PCB Copper Sizes Copper Size (mm2) 01 50 100 300 500 1 JA (C/W) 170 152 146 134 131 Device soldered to narrow traces. The typical JB value is 42.8C/W. Rev. 0 | Page 14 of 20 ADP122/ADP123 JUNCTION TEMPERATURE CALCULATIONS 140 TJ MAX 120 120 ILOAD = 300mA 100 80 60 ILOAD = 100mA 40 20 ILOAD = 1mA 0 0.5 1.0 1.5 ILOAD = 10mA 08399-128 140 TJ MAX JUNCTION TEMPERATURE (C) JUNCTION TEMPERATURE (C) ILOAD = 300mA 100 80 60 40 20 0 0.5 ILOAD = 150mA ILOAD = 150mA ILOAD = 100mA ILOAD = 25mA ILOAD = 25mA ILOAD = 1mA ILOAD = 10mA 2.0 2.5 3.0 1.0 1.5 2.0 2.5 3.0 VOUT - VIN (V) VOUT - VIN (V) Figure 34. Junction Temperature vs. Power Dissipation, 500 mm2 of PCB Copper, TA = 25C 140 TJ MAX 120 Figure 37. Junction Temperature vs. Power Dissipation, 500 mm2 of PCB Copper, TA = 50C 140 TJ MAX 120 JUNCTION TEMPERATURE (C) ILOAD = 300mA 100 80 60 ILOAD = 100mA 40 20 ILOAD = 1mA 0 0.5 1.0 1.5 2.0 ILOAD = 10mA 08399-129 JUNCTION TEMPERATURE (C) ILOAD = 300mA 100 80 60 40 20 0 0.5 ILOAD = 25mA ILOAD = 150mA ILOAD = 150mA ILOAD = 100mA ILOAD = 25mA ILOAD = 1mA ILOAD = 10mA 2.5 3.0 1.0 1.5 2.0 2.5 3.0 VOUT - VIN (V) VOUT - VIN (V) Figure 35. Junction Temperature vs. Power Dissipation, 100 mm2 of PCB Copper, TA = 25C Figure 38. Junction Temperature vs. Power Dissipation, 100 mm2 of PCB Copper, TA = 50C 140 TJ MAX 120 140 TJ MAX 120 JUNCTION TEMPERATURE (C) JUNCTION TEMPERATURE (C) ILOAD = 300mA 100 80 60 40 20 ILOAD = 1mA 0 0.5 1.0 1.5 ILOAD = 10mA 08399-130 ILOAD = 300mA 100 80 60 40 20 0 0.5 ILOAD = 150mA ILOAD = 150mA ILOAD = 100mA ILOAD = 25mA ILOAD = 100mA ILOAD = 25mA ILOAD = 1mA ILOAD = 10mA 2.0 2.5 3.0 1.0 1.5 2.0 2.5 3.0 VOUT - VIN (V) VOUT - VIN (V) Figure 36. Junction Temperature vs. Power Dissipation, 0 mm2 of PCB Copper, TA = 25C Figure 39. Junction Temperature vs. Power Dissipation, 0 mm2 of PCB Copper, TA = 50C Rev. 0 | Page 15 of 20 08399-133 08399-132 08399-131 ADP122/ADP123 140 120 PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS Heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the ADP122/ADP123. However, as shown in Table 6, a point of diminishing returns eventually is reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. The input capacitor should be placed as close as possible to the VIN and GND pins, and the output capacitor should be placed as close as possible to the VOUT and GND pins. Use of 0402 or 0603 size capacitors and resistors achieves the smallest possible footprint solution on boards where the area is limited. JUNCTION TEMPERATURE (C) 100 80 60 40 20 0 0.4 ILOAD = 1mA ILOAD = 10mA ILOAD = 50mA ILOAD = 100mA ILOAD = 150mA ILOAD = 250mA ILOAD = 300mA TJ MAX 0.8 1.2 1.6 VIN - VOUT (V) 2.0 2.4 2.8 Figure 40. Junction Temperature vs. Power Dissipation, Board Temperature = 85C 08399-134 Rev. 0 | Page 16 of 20 ADP122/ADP123 Figure 41. Example ADP122 PCB Layout Figure 42. Example ADP123 PCB Layout Rev. 0 | Page 17 of 20 08399-042 08399-041 ADP122/ADP123 OUTLINE DIMENSIONS 2.90 BSC 5 4 1.60 BSC 1 2 3 2.80 BSC 0.95 BSC *0.90 MAX 0.70 MIN 1.90 BSC *1.00 MAX 0.20 0.08 8 4 0 0.60 0.45 0.30 100708-A 0.10 MAX 0.50 0.30 SEATING PLANE *COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. Figure 43. 5-Lead Thin Small Outline Transistor Package [TSOT] (UJ-5) Dimensions shown in millimeters ORDERING GUIDE Model ADP122AUJZ-2.5-R7 2 ADP122AUJZ-2.7-R72 ADP122AUJZ-2.8-R72 ADP122AUJZ-2.85-R72 ADP122AUJZ-2.9-R72 ADP122AUJZ-3.0-R72 ADP122AUJZ-3.3-R72 ADP123AUJZ-R72 ADP122-3.3-EVALZ2 ADP123-EVALZ2 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Output Voltage (V) 1 2.5 2.7 2.8 2.85 2.9 3.0 3.3 0.8 to 5.0 (Adjustable) 3.3 Adjustable Package Description 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT 5-Lead TSOT Evaluation Board Evaluation Board Package Option UJ-5 UJ-5 UJ-5 UJ-5 UJ-5 UJ-5 UJ-5 UJ-5 Branding LE6 LE9 LEA LEC LED LEE LEF LEG Up to 31 fixed-output voltage options from 1.75 V to 3.3 V are available. For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative. 2 Z = RoHS Compliant Part. Rev. 0 | Page 18 of 20 ADP122/ADP123 NOTES Rev. 0 | Page 19 of 20 ADP122/ADP123 NOTES (c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08399-0-10/09(0) Rev. 0 | Page 20 of 20 |
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